T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Hardware design considerations
Table 135. Valid SerDes RCW encodings and reference clocks (continued)
SerDes protocol (given
lane)
Valid reference
clock
frequency
Legal setting for
SRDS_PRTCL_S1
Legal setting
for
SRDS_PLL_RE
F_CLK_SEL_S1
Legal setting for
SRDS_DIV_*_S1
Notes
1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interface such as
SATA, SGMII, SGMII 2.5G, 1000Base-KX, is used concurrently on the same SerDes PLL, spread-spectrum clocking is not
permitted.
2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the
SATA IP itself. It is possible for software to set each SATA at different rate.
4.1.8 eSDHC SDR mode clock select
The eSDHC SDR mode is asynchronous to the platform.
This table describes the clocking options that may be applied to the eSDHC SDR mode.
The clock selection is determined by the binary value of the RCW Clocking
Configuration field HWA_CGA_M1_CLK_SEL.
Table 136. eSDHC SDR mode clock select
Binary value of HWA_CGA_M1_CLK_SEL
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
Notes:
1. For asynchronous mode, max frequency, see table "Processor clocking specifications" in the chip reference manual.
2. For SDR104 and HS200 modes, CGA1 PLL should be set to provide a minimum of 1200MHz.
3. For SDR50 mode, Cluster PLL should be set to provide a minimum of 600MHz
Reserved
Cluster group A PLL 1/1
Cluster group A PLL 1/2
Cluster group A PLL 1/3
Cluster group A PLL 1/4
Reserved
Cluster group A PLL 2/2
Cluster group A PLL 2/3
eSDHC SDR mode frequency
1
4.1.9 Frequency options
This section discusses interface frequency options.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
166
Freescale Semiconductor, Inc.
