T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Hardware design considerations
1 kΩ
OV
DD
From target
board sources
(if any)
HRESET_B
PORESET_B
7
10 kΩ
HRESET_B
6
10 kΩ
PORESET_B
1
COP_HRESET_B
13
COP_SRESET_B
11
B
A
5
1
3
5
7
9
11
13
15
2
4
6
8
10
12
10 kΩ
10 kΩ
10 kΩ
10 kΩ
COP_TRST_B
COP_VDD_SENSE
2
NC
COP_CHKSTP_OUT_B
10 kΩ
COP_CHKSTP_IN_B
COP_TMS
COP_TDO
COP_TDI
COP_TCK
NC
NC
4
10 kΩ
10 Ω
TRST_B
1
4
6
COP header
5
15
14
3
CKSTP_OUT_B
KEY
No pin
16
COP connector
physical pinout
8
9
1
3
7
2
10
12
16
System logic
TMS
TDO
TDI
TCK
Notes:
1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
6. Asserting HRESET_B causes a hard reset on the device
7. This is an open-drain output gate.
Figure 81. Legacy JTAG Interface Connection
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
Freescale Semiconductor, Inc.
179
