T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Pin assignments
1. Functionally, this pin is an output or an input, but structurally it is an I/O because it
either sample configuration input during reset, is a muxed pin, or has other manufacturing
test functions. This pin is therefore be described as an I/O for boundary scan.
2. During reset this output signal is actively driven rather than being tri-stated.
3. MDIC[0] is grounded through a 162Ω precision 1% resistor and MDIC[1] is connected
to GV1
DD
through a 162Ω precision 1% resistor. For either full or half driver strength
calibration of DDR IOs, use the same MDIC resistor value of 162Ω. Memory controller
register setting can be used to determine automatic calibration is done to full or half drive
strength. These pins are used for automatic calibration of the DDR3L/DDR4 IOs. The
MDIC[0:1] pins must be connected to 162Ω precision 1% resistors.
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that
is enabled only when the processor is in its reset state. This pull-up is designed such that
it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to
be high after reset, and if there is any device on the net that might pull down the value of
the net at reset, a pull-up or active driver is needed.
5. Pin must
NOT
be pulled down during power-on reset. This pin may be pulled up,
driven high, or if there are any externally connected devices, left in tristate. If this pin is
connected to a device that pulls down during reset, an external pull-up is required to drive
this pin to a safe state during reset.
6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the
respective power supply.
7. This pin is an open-drain signal.
8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective
power supply.
9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.
10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to
the respective power supply for normal operation.
11. This pin requires a 200Ω pull-up to respective power-supply.
12. Do not connect. These pins should be left floating.
14. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a
valid Transmit Enable before it is actively driven.
15. These pins must be pulled to ground (GND).
16. This pin requires a 698Ω pull-up to respective power-supply.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
Freescale Semiconductor, Inc.
45
