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Home > Data Sheet > T1022NXE7MQA
T1022NXE7MQA

T1022NXE7MQA

Model T1022NXE7MQA
Description 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780
PDF file Total 197 pages (File size: 1M)
Chip Manufacturer PHILIPS
Hardware design considerations
• F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
Bulk
and
Bulk
and
decoupling
decoupling
capacitors
capacitors
F1
V
DD
/ V
DDC
C1
C1
USB_SV
DD
GND
Figure 79. USB_SV
DD
power supply filter circuit
4.3 Decoupling recommendations
Due to large address and data buses, and high operating frequencies, the device can
generate transient power surges and high frequency noise in its power supply, especially
while driving large capacitive loads. This noise must be prevented from reaching other
components in the chip system, and the chip itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one
decoupling capacitor at each V
DD
, V
DDC
, CV
DD
, OnV
DD
, DV
DD
, EV
DD
, GnV
DD
, and
LnV
DD
pin of the device. These decoupling capacitors should receive their power from
separate V
DD
, CV
DD
, OnV
DD
, DV
DD
, EV
DD
, GnV
DD
, LnV
DD
, and GND power planes in
the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount
technology) capacitors should be used to minimize lead inductance, preferably 0402 or
0201 sizes.
As presented in
it is recommended that there
be several bulk storage capacitors distributed around the PCB, feeding the V
DD
, V
DDC
and other planes (for example, CV
DD
, OnV
DD
, DV
DD
, EV
DD
, GnV
DD
, and LnV
DD
), to
enable quick recharging of the smaller chip capacitors.
4.4 SerDes block power supply decoupling recommendations
The SerDes block requires a clean, tightly regulated source of power (S1V
DD
and
X1V
DD
) to ensure low jitter on transmit and reliable recovery of data in the receiver. An
appropriate decoupling scheme is outlined below.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
Freescale Semiconductor, Inc.
175
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