T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
Table 23. DDR3L SDRAM interface DC electrical characteristics (G1V
DD
= 1.35 V)
1, 9
(continued)
Parameter
Notes:
1. G1V
DD
is expected to be within 50 mV of the DRAM's voltage supply at all times. The voltage supply of DRAM and
memory controller may or may not be from the same source.
2. D1_MV
REF
is expected to be equal to 0.5 x G1V
DD
and to track G1V
DD
DC variations as measured at the receiver. Peak-
to-peak noise on D1_MV
REF
may not exceed the D1_MV
REF
DC level by more than ±1% of G1V
DD
(that is, ±13.5mV).
3. V
TT
is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to D1_MV
REF
with a min value of D1_MV
REF
- 0.04 and a max value of D1_MV
REF
+ 0.04. V
TT
should track variations
in the DC level of D1_MV
REF
.
4. The voltage regulator for D1_MV
REF
must meet the specifications stated in
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ V
OUT
≤ G1V
DD
.
7. See the IBIS model for the complete output IV curve characteristics.
8. I
OH
and I
OL
are measured at G1V
DD
= 1.283 V.
9. For recommended operating conditions, see
Symbol
Min
Max
Unit
Note
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR4 SDRAM.
Table 24. DDR4 SDRAM interface DC electrical characteristics (G1V
DD
= 1.2
V)
1, 8
Parameter
Input low
Input high
Output high current (V
OUT
= 0.57V)
Output low current (V
OUT
=0.57V)
I/O leakage current
Notes:
1. G1V
DD
is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track G1VDD/2.
3. Input capacitance load for MDQ, MDQS, and MDQS_B are available in the IBIS models.
4. I
OH
and I
OL
are measured at G1V
DD
= 1.14 V.
5. Refer to the IBIS model for the complete output IV curve characteristics.
6. Output leakage is measured with all outputs disabled, 0 V ≤ V
OUT
≤ G1V
DD
.
7. Internal Vref for data bus must be set to 0.7 x G1VDD.
8. For recommended operating conditions, see
Symbol
V
IL
V
IH
I
OH
I
OL
I
OZ
-
0.7 x G1V
DD
+
0.175
-
20.7
-100
Min
-
-20.7
-
100
Max
0.7 x G1V
DD
- 0.175 V
V
mA
mA
μA
Unit
Note
3, 7
3, 7
4, 5
4, 5
6
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
Freescale Semiconductor, Inc.
69
