T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
Table 96. I
2
C AC timing specifications
5
(continued)
Parameter
Capacitive load for each bus line
Notes:
1. The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
I2DVKH
symbolizes I
2
C timing (I2) with
respect to the time data input signals (D) reaching the valid state (V) relative to the t
I2C
clock reference (K) going to the high
(H) state or setup time. Also, t
I2SXKL
symbolizes I
2
C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the t
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
I2PVKH
symbolizes I
2
C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the t
I2C
clock
reference (K) going to the high (H) state or setup time.
2. The requirements for I
2
C frequency calculation must be followed. See
Determining the I
2
C Frequency Divider Ratio for
SCL
(AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the chip acts as the I
2
C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
chip as transmitter, see
Determining the I
2
C Frequency Divider Ratio for SCL
(AN2919).
4. The maximum t
I2OVKL
has to be met only if the device does not stretch the LOW period (t
I2CL
) of the SCL signal.
5. For recommended operating conditions, see
Symbol
1
Cb
-
Min
400
Max
Unit
pF
-
Notes
This figure provides the AC test load for the I
2
C.
Output
Z
0
= 50 Ω
R
L
= 50 Ω
DV
DD
/2
Figure 56. I
2
C AC test load
This figure shows the AC timing diagram for the I
2
C bus.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
130
Freescale Semiconductor, Inc.
