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Home > Data Sheet > T1022NXE7MQA
T1022NXE7MQA

T1022NXE7MQA

Model T1022NXE7MQA
Description 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780
PDF file Total 197 pages (File size: 1M)
Chip Manufacturer PHILIPS
Hardware design considerations
1 kΩ
OV
DD
From target
board sources
(if any)
HRESET_B
PORESET_B
5
10 kΩ
HRESET_B
4
10 kΩ
PORESET_B
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
22
20, 25, 27, 31,
32, 33, 37, 38,
39, 40, 43, 44,
45, 46, 49, 50,
51, 52, 55, 56,
57, 58, 61, 62,
63, 64, 67, 68,
69, 70
Reset
10 kΩ
B
NC
3
A
10 kΩ
10 kΩ
AURORA_TRST_B
VIO VSense
2
AURORA_TMS
AURORA_TDO
AURORA_TDI
AURORA_TCK
Vendor I/O 5 (Aurora_HRESET_B)
CLK_P
100 nF
CLK_N
100 nF
Vendor I/O 2 (Aurora_Event_Out_B)
Vendor I/O 1 (Aurora_Event_In_B)
Vendor I/O 0 (Aurora_HALT_B)
TX0_P
TX0_N
TX1_P
TX1_N
RX0_P
RX0_N
RX1_P
RX1_N
7
6
REF_CLK_P
REF_CLK_N
6
REF_CLK1_P
REF_CLK1_N
10 kΩ
1 kΩ
TMS
TDO
TDI
TCK
SD1_REF_CLKn_P
SD1_REF_CLKn_N
EVT[4]
EVT[1]
EVT[0]
SD1_TX4_P
SD1_TX4_N
7
0.01 uF
0.01 uF
SD1_RX4_P
SD1_RX4_N
TRST_B
1
12
2
6
10
8
Aurora Header
4
34
26
28
18
16
14
1
3
7
9
13
15
19
21
5, 11, 17, 23, 24,
29, 30, 35, 36, 41,
42, 47, 48, 53, 54,
59, 60, 65, 66
Duplex 70 Connector
Physical Pinout
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
4. Asserting HRESET_B causes a hard reset on the device
5. This is an open-drain output gate.
6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source.
7. RX1_P/RX1_N and TX1_P/TX1_N can be left floating at Aurora Header
Figure 85. Aurora 70 pin connector duplex interface connection
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
184
Freescale Semiconductor, Inc.
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