T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
Table 107. SD1_REF_CLKn_P and SD1_REF_CLKn_N input
clock requirements (S1V
DD
n
= 1.0 V)
1
Parameter
SD1_REF_CLKn_P/SD1_REF_CLKn_N frequency
range
SD1_REF_CLKn_P/SD1_REF_CLKn_N clock
frequency tolerance
SD1_REF_CLKn_P/SD1_REF_CLKn_N clock
frequency tolerance
SD1_REF_CLKn_P/SD1_REF_CLKn_N reference
clock duty cycle
SD1_REF_CLKn_P/SD1_REF_CLKn_N max
deterministic peak-to-peak jitter at 10
-6
BER
SD1_REF_CLKn_P/SD1_REF_CLKn_N total
reference clock jitter at 10
-6
BER (peak-to-peak jitter
at refClk input)
SD1_REF_CLKn_P/SD1_REF_CLKn_N 10 kHz to
1.5 MHz RMS jitter
SD1_REF_CLKn_P/SD1_REF_CLKn_N > 1.5 MHz
to Nyquist RMS jitter
Symbol
t
CLK_REF
t
CLK_TOL
t
CLK_TOL
t
CLK_DUTY
t
CLK_DJ
t
CLK_TJ
-
-300
-100
40
-
-
Min
Typ
100/125
-
-
50
-
-
-
300
100
60
42
86
Max
Unit
MHz
ppm
ppm
%
ps
ps
2
3
4
5
-
6
Notes
t
REFCLK-LF-RMS
t
REFCLK-HF-RMS
-
-
0.6
150
-
-
-
-
-
-
-
-
3
3.1
4
-
-150
20
ps
RMS
ps
RMS
V/ns
mV
mV
%
7
7
9
5
5
10, 11
SD1_REF_CLKn_P/SD1_REF_CLKn_N rising/falling t
CLKRR/
t
CLKFR
edge rate
Differential input high voltage
Differential input low voltage
Rising edge rate (SD1REF_CLKn_P) to falling edge
rate (SD1_REF_CLKn_N) matching
V
IH
V
IL
Rise-Fall
Matching
1. For recommended operating conditions, see
2.
Caution:
Only 100 and 125 have been tested.In-between values do not work correctly with the rest of the system.
3. For PCI Express(2.5, 5 GT/s)
4. For SGMII, 2.5G SGMII
5. Measurement taken from differential waveform
6. Limits from PCI Express CEM Rev 2.0
7. For PCI Express-5 GT/s, per PCI Express base specification rev 3.0
9. Measured from -150 mV to +150 mV on the differential waveform (derived from SD1_REF_CLKn_P minus
SD1_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV
measurement window is centered on the differential zero crossing. See
10. Measurement taken from single-ended waveform
11. Matching applies to rising edge for SD1_REF_CLKn_P and falling edge rate for SD1_REF_CLKn_N. It is measured using
a ±75 mV window centered on the median cross point where SD1_REF_CLKn_P rising meets SD1_REF_CLKn_N falling.
The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations.
The rise edge rate of SD1_REF_CLKn_P must be compared to the fall edge rate of SD1_REF_CLKn_N, the maximum
allowed difference should not exceed 20% of the slowest edge rate. See
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
144
Freescale Semiconductor, Inc.
