T1022NXE7MQA
| Model | T1022NXE7MQA |
| Description | 32-BIT, 1200MHz, RISC PROCESSOR, PBGA780 |
| PDF file | Total 197 pages (File size: 1M) |
| Chip Manufacturer | PHILIPS |
Electrical characteristics
Table 27. DDR4 SDRAM interface input AC timing specifications
1
(continued)
Parameter
Notes:
1. For recommended operating conditions, see
Symbol
Min
Max
Unit
Notes
This table provides the input AC timing specifications for the DDR controller when
interfacing to DDR3L and DDR4 SDRAM.
Table 28. DDR4 and DDR3L SDRAM interface input AC timing
specifications
3
Parameter
Controller Skew for MDQS-MDQ/MECC
1600 MT/s data rate
1300 MT/s data rate
1200 MT/s data rate
1000 MT/s data rate
Tolerated Skew for MDQS-MDQ/MECC
1600 MT/s data rate
1300 MT/s data rate
1200 MT/s data rate
1000 MT/s data rate
t
DISKEW
-200
-250
-275
-300
200
250
275
300
Symbol
t
CISKEW
-112
-125
-142
-170
112
125
142
170
ps
2
2
2, 4
2, 4
Min
Max
ps
1
1
1, 4
1, 4
Unit
Notes
1. t
CISKEW
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
DISKEW
.This can be
determined by the following equation: t
DISKEW
= ±(T ÷ 4 - abs(t
CISKEW
)) where T is the clock period and abs(t
CISKEW
) is the
absolute value of t
CISKEW
.
3. For recommended operating conditions, see
4. DDR3L only
This figure shows the DDR4 and DDR3L SDRAM interface input timing diagram.
QorIQ T1042, T1022 Data Sheet, Rev. 2, 06/2015
Freescale Semiconductor, Inc.
71
