U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Table 2-46 •
STC Bits Function
Name
STC
Bits
[7:0]
Sample time control
Function
Sample time is computed based on the period of ADCCLK.
Distribution Phase
The second phase is called the distribution phase. During distribution phase, the ADC computes the
equivalent digital value from the value stored in the input capacitor. In this phase, the output signal
SAMPLE goes back to '0', indicating the sample is completed; but the BUSY signal remains '1', indicating
the ADC is still busy for distribution. The distribution time depends strictly on the number of bits. If the
ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed.
describes the distribution
time.
t
distrib
=
N
×
t
ADCCLK
EQ 21
N: Number of bits
Post-Calibration Phase
The last phase is the post-calibration phase. This is an optional phase. The post-calibration phase takes
two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is completed.
If the post-calibration phase is skipped, then the BUSY signal goes to '0' after distribution phase. As soon
as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating the digital result is available on
the RESULT output signals. DATAVAILD will remain '1' until the next ADCSTART is asserted. Microsemi
recommends enabling post-calibration to compensate for drift and temperature-dependent effects. This
ensures that the ADC remains consistent over time and with temperature. The post-calibration phase is
enabled by bit 3 of the Mode register.
describes the post-calibration time.
t
post-cal
=
MODE
[
3
] × (
2
×
t
ADCCLK
)
EQ 22
MODE[3]: Bit 3 of the Mode register, described in
The calculation for the conversion time for the ADC is summarized in
t
conv
= t
sync_read
+ t
sample
+ t
distrib
+ t
post-cal
+ t
sync_write
EQ 23
t
conv
: conversion time
t
sync_read
: maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the
worst case is a period of SYSCLK, t
SYSCLK
.
t
sample
: Sample time
t
distrib
: Distribution time
t
post-cal
: Post-calibration time
t
sync_write
: Maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the
worst case is a period of SYSCLK, t
SYSCLK
.
Intra-Conversion
Performing a conversion during power-up calibration is possible but should be avoided, since the
performance is not guaranteed, as shown in
This is described as intra-
conversion.
shows intra-conversion (conversion that starts during power-up
calibration).
Injected Conversion
A conversion can be interrupted by another conversion. Before the current conversion is finished, a
second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion
is issued before the current conversion is completed, the current conversion would be dropped and the
ADC would start the second conversion on the rising edge of the SYSCLK. This is known as injected
conversion. Since the ADC is synchronous, the minimum time to issue a second conversion is two clock
cycles of SYSCLK after the previous one.
shows injected conversion
2- 11 2
R e visio n 3
