U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Datasheet Information
Revision
Revision 2
(continued)
Changes
The Y security option and Licensed DPA Logo was added to the
The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR
34721).
The
is new (SAR 34693).
The following information was added before
In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be
connected to GND and the XTAL2 pin should be left floating (SAR 24119).
was updated. A note was added
indicating that when the CCC/PLL core is generated by Microsemi core generator
software, not all delay values of the specified delay increments are available (SAR
34814).
A note was added to
stating that the user is only required to instantiate the
VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator
to be different from the default, or employ user logic to shut the voltage regulator off
(SAR 21773).
Page
VPUMP was incorrectly represented as VPP in several places. This was corrected to
VPUMP in the
and
through
(21963).
Additional information was added to the Flash Memory Block
including an explanation of the fact that a copy-page operation takes no less
than 55 cycles (SAR 26338).
The
was revised to refer to
and
rather than stating 20 MHz as the
maximum FlashROM access clock and 10 ns as the time interval for D0 to become
valid or invalid (SAR 22105).
The following figures were deleted (SAR 29991). Reference was made to a new
application note,
s,
which covers these cases in detail (SAR 34862).
Figure 2-55 • Write Access after Write onto Same Address
Figure 2-56 • Read Access after Write onto Same Address
Figure 2-57 • Write Access after Read onto Same Address
The port names in the SRAM
SRAM
tables,
and
the FIFO
tables were revised to ensure consistency with the
software names (SAR 35753).
In several places throughout the datasheet, GNDREF was corrected to
ADCGNDREF (SAR 20783):
The following note was added below
When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad
drive strength ceases and becomes a 1 µA sink into the Fusion device. (SAR
24796).
5-2
R e vi s i o n 3
