U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
details the settings available to either power down or enable the prescaler associated with the
analog inputs AV, AC, and AT.
Table 2-61 •
Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)
Control Lines Bx[7]
0
1
Prescaler Op Amp
Power-down
Operational
details the settings available to enable the Current Monitor Block associated with the AC pin.
Table 2-62 •
Current Monitor Input Switch Control Truth Table—AV (x = 0)
Control Lines B0[4]
0
1
Current Monitor Input Switch
Off
On
details the settings available to configure the drive strength of the gate drive when not in high-
drive mode.
Table 2-63 •
Low-Drive Gate Driver Current Truth Table (AG)
Control Lines B2[3]
0
0
1
1
Control Lines B2[2]
0
1
0
1
Current (µA)
1
3
10
30
details the settings available to set the polarity of the gate driver (either p-channel- or
n-channel-type devices).
Table 2-64 •
Gate Driver Polarity Truth Table (AG)
Control Lines B2[6]
0
1
Gate Driver Polarity
Positive
Negative
details the settings available to turn on the Gate Driver and set whether high-drive mode is on
or off.
Table 2-65 •
Gate Driver Control Truth Table (AG)
Control Lines B2[7]
0
0
1
1
GDON
0
1
0
1
Gate Driver
Off
Low drive on
Off
High drive on
details the settings available to turn on and off the chip internal temperature monitor.
Note:
For the internal temperature monitor to function, Bit 0 of Byte 2 for all 10 Quads must be set.
Table 2-66 •
Internal Temperature Monitor Control Truth Table
Control Lines B2[0]
0
1
PDTMB
0
1
Chip Internal Temperature Monitor
Off
On
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R e visio n 3
