U1AFS250-2FG256YI
Model | U1AFS250-2FG256YI |
Description | Field Programmable Gate Array, |
PDF file | Total 334 pages (File size: 18M) |
Chip Manufacturer | MICROSEMI |
Device Architecture
Output DDR
Data_F
(from core)
CLK
CLKBUF
Data_R
(from core)
CLR
INBUF
A
FF1
B
C
D
FF2
B
C
1
0
E
OUTBUF
Out
DDR_OUT
Figure 2-144 •
Output DDR Timing Model
Table 2-181 •
Parameter Definitions
Parameter Name
t
DDROCLKQ
t
DDROCLR2Q
t
DDROREMCLR
t
DDRORECCLR
t
DDROSUD1
t
DDROSUD2
t
DDROHD1
t
DDROHD2
Parameter Definition
Clock-to-Out
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
Measuring Nodes (From, To)
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
2- 22 4
R e visio n 3