U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Output Enable Register
t
OECKMPWH
t
OECKMPWL
CLK
50%
50%
t
OESUD
t
OEHD
50%
50%
50%
50%
50%
D_Enable
1
50%
0 50%
Enable
50%
t
OEWPRE
t
OEHE
t
OESUE
50%
t
OERECPRE
50%
t
OEREMPRE
50%
t
OEREMCLR
50%
Preset
t
OEWCLR
Clear
t
OEPRE2Q
EOUT
50%
t
OECLKQ
50%
50%
t
OERECCLR
50%
t
OECLR2Q
50%
Figure 2-141 •
Output Enable Register Timing Diagram
Timing Characteristics
Table 2-178 •
Output Enable Register Propagation Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
OECLKQ
t
OESUD
t
OEHD
t
OESUE
t
OEHE
t
OECLR2Q
t
OEPRE2Q
t
OEREMCLR
t
OERECCLR
t
OEREMPRE
t
OERECPRE
t
OEWCLR
t
OEWPRE
t
OECKMPWH
t
OECKMPWL
Description
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
–2
–1
Std.
0.59
0.42
0.00
0.58
0.00
0.89
0.89
0.00
0.30
0.00
0.30
0.30
0.30
0.48
0.43
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.44 0.51
0.31 0.36
0.00 0.00
0.44 0.50
0.00 0.00
0.67 0.76
0.67 0.76
0.00 0.00
0.22 0.25
0.00 0.00
0.22 0.25
Asynchronous Clear Minimum Pulse Width for the Output Enable 0.22 0.25
Register
Asynchronous Preset Minimum Pulse Width for the Output Enable 0.22 0.25
Register
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
0.36 0.41
0.32 0.37
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 3
2- 221
