U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Table 2-175 •
Parameter Definitions and Measuring Nodes
Parameter Name
t
O CL KQ
t
OSUD
t
OHD
t
OSUE
t
OHE
t
OCLR2Q
t
OREMCLR
t
ORECCLR
t
OECLKQ
t
OESUD
t
OEHD
t
OESUE
t
OEHE
t
OECLR2Q
t
OEREMCLR
t
OERECCLR
t
ICLKQ
t
ISUD
t
IHD
t
ISUE
t
IHE
t
ICLR2Q
t
IREMCLR
t
IRECCLR
Parameter Definition
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Measuring Nodes
(from, to)*
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
JJ, HH
KK, HH
KK, HH
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
Note:
*See
for more information.
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