U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
CCC and PLL Characteristics
Timing Characteristics
Table 2-12 •
Fusion CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
IN_CCC
Clock Conditioning Circuitry Output Frequency f
OUT_CCC
Delay Increments in Programmable Delay Blocks
1, 2
Number of Programmable Values in Each Programmable
Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
CCC_OUT
Min.
1.5
0.75
160
3
32
1.5
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
Acquisition Time
Tracking Jitter
4
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
1, 2
Delay Range in Block: Programmable Delay 2
1, 2
Delay Range in Block: Fixed Delay
1, 2
Notes:
1. This delay is a function of voltage and temperature. See
for deratings.
2. T
J
= 25°C, VCC = 1.5 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
Typ.
Max.
350
350
Unit
MHz
MHz
ps
ns
3 Global
Networks
Used
1.00%
1.50%
2.25%
3.50%
300
6.0
1.6
0.8
µs
ms
ns
ns
%
ns
ns
ns
1.00%
1.50%
2.25%
3.50%
48.5
0.6
0.025
2.2
51.5
5.56
5.56
2- 30
R e visio n 3
