U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Table 2-102 •
Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
VIL
Min.
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Max.
V
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
Min.
V
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VIH
Max.
V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
VOL
Max.
V
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
VOH
Min.
V
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
IOL IOH
mA mA
4
8
12
16
24
2
4
6
8
12
16
24
2
4
6
8
4
8
12
16
24
2
4
6
8
12
16
24
2
4
6
8
IOSL
Max.
mA
3
27
54
109
127
181
27
27
54
54
109
127
181
27
27
54
54
IOSH
Max.
mA
3
25
51
103
132
268
25
25
51
51
103
132
268
25
25
51
51
IIL
1
IIH
2
µA
4
µA
4
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Applicable to Pro I/O Banks
Applicable to Advanced I/O Banks
Applicable to Standard I/O Banks
Test Point
Data Path
35 pF
R=1k
Test Point
Enable Path
R to VCCI for t
LZ
/ t
ZL
/ t
ZLS
R to GND for t
HZ
/ t
ZH
/ t
ZHS
35 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
35 pF for t
HZ
/ t
LZ
Figure 2-119 •
AC Loading
Table 2-103 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
3.3
Measuring Point* (V)
1.4
VREF (typ.) (V)
–
C
LOAD
(pF)
35
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
2- 17 8
R e visio n 3
