U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Revision
Advance v1.6
(August 2008)
Changes
The title of the datasheet changed from Actel Programmable System Chips to Actel
Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip
were changed to mixed signal FPGA.
Page
N/A
The references to the
Peripherals User’s Guide
in the
"No-Glitch MUX (NGMUX)" 2-32, 2-42
section
and
"Voltage Regulator Power Supply Monitor (VRPSM)" section
were
changed to
Fusion Handbook.
Advance v1.5
(July 2008)
The following bullet was updated from High-Voltage Input Tolerance: ±12 V to High-
Voltage Input Tolerance: 10.5 V to 12 V.
The following bullet was updated from Programmable 1, 3, 10, 30 µA and 25 mA
Drive Strengths to Programmable 1, 3, 10, 30
µ
A and 20 mA Drive Strengths.
This bullet was added to the
"Integrated A/D Converter (ADC) and Analog I/O"
section:
ADC Accuracy is Better than 1%
In the
"Integrated Analog Blocks and Analog I/Os" section,
±4 LSB was changed to
0.72. The following sentence was deleted:
The input range for voltage signals is from –12 V to +12 V with full-scale output
values from 0.125 V to 16 V.
In addition, 2°C was changed to 3°C:
"One analog input in each quad can be connected to an external temperature
monitor diode and achieves detection accuracy of ±3ºC."
The following sentence was deleted:
The input range for voltage signals is from –12 V to +12 V with full-scale output
values from 0.125 V to 16 V.
The title of the datasheet changed from Actel Programmable System Chips to Actel
Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip
were changed to mixed signal FPGA.
Advance v1.4
(July 2008)
Advance v1.3
(July 2008)
Advance v1.2
(May 2008)
In
Table 3-8 · Quiescent Supply Current
references were updated for I
DC2
and I
DC3
.
Characteristics
(IDDQ)1,
footnote
N/A
1-4
I
I
I
3-11
Footnote 3 and 4 were updated and footnote 5 is new.
The
"ADC Description" section
was significantly updated. Please review carefully.
Table 2-25 • Flash Memory Block Timing
was significantly updated.
The
"V
AREF
Analog Reference Voltage"
pin description section was significantly
update. Please review it carefully.
Table 2-45 • ADC Interface Timing
was significantly updated.
Table 2-56 • Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1),
and AT (x = 3)
was significantly updated.
The following sentence was deleted from the
"Voltage Monitor" section:
The Analog Quad inputs are tolerant up to 12 V + 10%.
The
"180-Pin QFN"
figure was updated. D1 to D4 are new and the figure was
changed to bottom view. The note below the figure is new.
3-3
2-102
2-55
2-226
2-110
2-131
2-86
Revision 3
5 -7
