U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output
buffer.
Table 2-150 •
Minimum and Maximum DC Input and Output Levels
HSTL
Class I
Drive
Strength
8 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
VIL
Min.
V
–0.3
Max.
V
Min.
V
VIH
Max.
V
3.6
VOL
Max.
V
0.4
VOH
Min.
V
VCCI – 0.4
IOL IOH IOSL IOSH IIL
1
IIH
2
mA mA
8
8
Max.
mA
3
39
Max.
mA
3
µA
4
µA
4
32
10
10
VREF – 0.1 VREF + 0.1
HSTL
Class I
Test Point
VTT
50
20 pF
Figure 2-128 •
AC Loading
Table 2-151 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
VREF – 0.1
Input High (V)
VREF + 0.1
Measuring Point* (V)
0.75
VREF (typ.) (V)
0.75
VTT (typ.) (V)
0.75
C
LOAD
(pF)
20
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
Timing Characteristics
Table 2-152 •
HSTL Class I
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
Speed
Grade
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
t
DP
3.18
2.70
2.37
t
DIN
0.04
0.04
0.03
t
PY
2.12
1.81
1.59
t
EOUT
0.43
0.36
0.32
t
ZL
3.24
2.75
2.42
t
ZH
3.14
2.67
2.35
t
LZ
t
HZ
t
ZLS
5.47
4.66
4.09
t
ZHS
5.38
4.58
4.02
Units
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
2- 20 6
R e visio n 3
