U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Features Supported on Pro I/Os
lists all features supported by transmitter/receiver for single-ended and differential I/Os.
Table 2-72 •
Fusion Pro I/O Features
Feature
Single-ended
and
voltage- •
referenced transmitter
features
•
•
•
•
Description
Hot insertion in every mode except PCI or 5 V input tolerant (these modes use
clamp diodes and do not allow hot insertion)
Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.
Weak pull-up and pull-down
Two slew rates
Skew between output buffer enable/disable time: 2 ns delay (rising edge) and
0 ns delay (falling edge); see
for more information
Five drive strengths
5 V–tolerant receiver ("5
LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5
High performance (Table
Schmitt trigger option
ESD protection
Programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns
with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)
High performance (Table
Separate ground planes, GND/GNDQ, for input buffers only to avoid output-
induced noise in the input circuitry
Programmable Delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns
with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)
High performance (Table
Separate ground planes, GND/GNDQ, for input buffers only to avoid output-
induced noise in the input circuitry
Two I/Os and external resistors are used to provide a CMOS-style LVDS,
BLVDS, M-LVDS, or LVPECL transmitter solution.
Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.
Weak pull-up and pull-down
Fast slew rate
ESD protection
High performance (Table
Programmable delay: 0.625 ns with '000' setting, 6.575 ns with '111' setting,
0.85-ns intermediate delay increments (at 25°C, 1.5 V)
Separate input buffer ground and power planes to avoid output-induced noise
in the input circuitry
•
•
•
•
Single-ended receiver features
•
•
•
•
•
Voltage-referenced
receiver features
differential •
•
•
CMOS-style LVDS,
M-LVDS, or LVPECL
transmitter
BLVDS, •
•
•
•
LVDS/LVPECL differential
receiver features
•
•
•
•
Revision 3
2- 139
