U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Table 2-174 •
Parameter Definitions and Measuring Nodes
Parameter
Name
t
OCLKQ
t
OSUD
t
OHD
t
OSUE
t
OHE
t
OPRE2Q
t
OREMPRE
t
ORECPRE
t
OECLKQ
t
OESUD
t
OEHD
t
OESUE
t
OEHE
t
OEPRE2Q
t
OEREMPRE
t
OERECPRE
t
ICLKQ
t
ISUD
t
IHD
t
ISUE
t
IHE
t
IPRE2Q
t
IREMPRE
t
IRECPRE
Parameter Definition
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Measuring Nodes
(from, to)*
H, DOUT
F, H
F, H
G, H
G, H
L,DOUT
L, H
L, H
H, EOUT
J, H
J, H
K, H
K, H
I, EOUT
I, H
I, H
A, E
C, A
C, A
B, A
B, A
D, E
D, A
D, A
Note:
*See
for more information.
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