Home > Data Sheet > U1AFS250-2FG256YI

U1AFS250-2FG256YI

Model	U1AFS250-2FG256YI
Description	Field Programmable Gate Array,
PDF file	Total 334 pages (File size: 18M)
Chip Manufacturer	MICROSEMI

Download (18M)

Fusion Family of Mixed Signal FPGAs

Analog Configuration MUX

The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter.

Microsemi Libero SoC will generate IP that will load and configure the Analog Block via the ACM.

However, users are not limited to using the Libero SoC IP. This section provides a detailed description of

the ACM's register map, truth tables for proper configuration of the Analog Block and RTC, as well as

timing waveforms so users can access and control the ACM directly from their designs.

The Analog Block contains four 8-bit latches per Analog Quad that are initialized through the ACM.

These latches act as configuration bits for Analog Quads. The ACM block runs from the core voltage

supply (1.5 V).

Access to the ACM is achieved via 8-bit address and data busses with enables. The pin list is provided in

Table 2-36 on page 2-81.

The ACM clock speed is limited to a maximum of 10 MHz, more than sufficient

to handle the low-bandwidth requirements of configuring the Analog Block and the RTC (sub-block of the

Analog Block).

Table 2-54

decodes the ACM address space and maps it to the corresponding Analog Quad and

configuration byte for that quad.

Table 2-54 •

ACM Address Decode Table for Analog Quad

ACMADDR [7:0] in

Decimal

COUNTER0

COUNTER1

COUNTER2

COUNTER3

COUNTER4

MATCHREG0

MATCHREG1

Name

–

AQ0

AQ1

AQ8

AQ9

Description

–

Byte 0

Byte 1

Byte 2

Byte 3

Byte 0

Byte 3

Byte 0

Byte 1

Byte 2

Byte 3

Undefined

Associated

Peripheral

Analog Quad

Undefined

Counter bits 7:0

Counter bits 15:8

Counter bits 23:16

Counter bits 31:24

Counter bits 39:32

Match register bits 7:0

Match register bits 15:8

RTC

Revision 3

2- 129

prev next