U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to
for a
simplified representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in
between
registers to implement single or differential data transmission to and from the FPGA core. The Designer
software sets these switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input
register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O
register combining must satisfy some rules.
I/O / Q0
1
Input
Reg
2
Input
Reg
Y
Pull-Up/Down
Resistor Control
To FPGA Core
I/O / Q1
CLR/PRE
3
Input
Reg
PAD
ICE
CLR/PRE
I/O / ICLK
Signal Drive Strength
and Slew-Rate Control
E = Enable Pin
A
I/O / D0
4
Output
OCE
Reg
From FPGA Core
I/O / D1 / ICE
CLR/PRE
5
Output
Reg
ICE
I/O / OCLK
I/O / OE
CLR/PRE
6
OCE Output
Enable
Reg
CLR/PRE
I/O / CLR or I/O / PRE / OCE
Note:
Fusion I/Os have registers to support DDR functionality (see the
for more information).
Figure 2-100 •
I/O Block Logical Representation
Revision 3
2- 141
