U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
t
PD
= 0.56 ns
Combinational Cell
Y
t
PD
= 0.49 ns
t
Dp
= 1.60 ns
I/O Module
(Non-Registered)
LVPECL (Pro IO banks)
Combinational Cell
Y
LVTTL/LVCMOS 3.3 V (Pro I/O banks)
t
DP
= 2.74 ns Output drive strength = 12 mA
High slew rate
t
PD
= 0.87 ns
I/O Module
Combinational Cell
(Non-Registered)
I/O Module
(Registered)
t
PY
= 1.22 ns
LVPECL
(Pro IO Banks)
D
Q
Combinational Cell
Y
Input LVTTL/LVCMOS
3.3 V (Pro IO banks)
t
ICLKQ
= 0.24 ns
t
ISUD
= 0.26 ns
t
PD
= 0.47 ns
Y
LVTTL/LVCMOS 3.3 V (Pro I/O banks)
Output drive strength = 24 mA
t
DP
= 2.39 ns High slew rate
t
PD
= 0.51 ns
I/O Module
(Non-Registered)
LVCMOS 1.5 V (Pro IO banks)
Output drive strength = 12 mA
t
DP
= 3.30 ns High slew
I/O Module
(Registered)
D
Q
GTL+ 3.3 V
t
DP
= 1.53 ns
t
CLKQ
= 0.55 ns
t
SUD
= 0.43 ns
IInput LVTTL/LVCMOS
3.3 V (Pro IO banks)
t
PY
= 0.90 ns
t
OCLKQ
= 0.59 ns
t
OSUD
= 0.31 ns
t
PY
= 0.90 ns
I/O Module
(Non-Registered)
LVDS,
BLVDS,
M-LVDS (Pro IO Banks)
t
PY
= 1.36 ns
Register Cell Combinational Cell
D
Q
Y
t
PD
= 0.47 ns
t
CLKQ
= 0.55 ns
t
SUD
= 0.43 ns
Input LVTTL/LVCMOS
3.3 V (Pro IO banks)
t
PY
= 0.90 ns
Register Cell
D
Q
Figure 2-115 •
Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (T
J
= 70°C),
Worst-Case VCC = 1.425 V
Revision 3
2- 163
