U1AFS250-2FG256YI
| Model | U1AFS250-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Timing Characteristics
Table 2-31 •
RAM4K9
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
AS
t
AH
t
ENS
t
ENH
t
BKS
t
BKH
t
DS
t
DH
t
CKQ1
t
CKQ2
t
C2CWWH1
t
C2CRWH1
t
C2CWRH1
t
RSTBQ
t
REMRSTB
t
RECRSTB
t
MPWRSTB
t
CYC
F
MAX
Notes:
1. For more information, refer to the application note
2. For the derating values at specific junction temperature and voltage supply levels, refer to
Description
Address setup time
Address hold time
REN, WEN setup time
REN, WEN hold time
BLK setup time
BL hold time
Input data (DIN) setup time
Input data (DIN) hold time
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
–2
–1
Std.
0.33
0.00
0.19
0.13
0.31
0.02
0.25
0.00
2.39
3.15
1.20
0.23
0.34
0.37
1.23
1.23
0.38
2.01
0.29
4.32
231
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
0.25 0.28
0.00 0.00
0.14 0.16
0.10 0.11
0.23 0.27
0.02 0.02
0.18 0.21
0.00 0.00
1.79 2.03
2.36 2.68
0.89 1.02
Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26
address—Applicable to Rising Edge
Address collision clk-to-clk delay for reliable read access after write on 0.45 0.38
same address—Applicable to Opening Edge
Address collision clk-to-clk delay for reliable write access after read on 0.49 0.42
same address— Applicable to Opening Edge
RESET Low to data out Low on DOUT (flow-through)
RESET Low to Data Out Low on DOUT (pipelined)
RESET removal
RESET recovery
RESET minimum pulse width
Clock cycle time
Maximum frequency
0.92 1.05
0.92 1.05
0.29 0.33
1.50 1.71
0.21 0.24
3.23 3.68
310
272
Revision 3
2- 69
