U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Device Family Overview
standards. In the family’s larger devices, the north bank is divided into two banks of digital Pro I/Os,
supporting a wide variety of single-ended, differential, and voltage-referenced I/O standards.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following applications:
•
•
•
Single-Data-Rate (SDR) applications
Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications
Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.
VersaTiles
The Fusion core consists of VersaTiles, which are also used in the successful ProASIC3 family. The
Fusion VersaTile supports the following:
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set and optional enable
Refer to
for the VersaTile configuration arrangement.
LUT-3 Equivalent
X1
X2
X3
D-Flip-Flop with Clear or Set
Data
CLK
CLR
Y
Enable D-Flip-Flop with Clear or Set
Data
CLK
Enable
CLR
Y
LUT-3
Y
D-FF
D-FFE
Figure 1-2 •
VersaTile Configurations
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the
for more information.
Note:
PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
The I/Os are controlled by the JTAG Boundary Scan register during programming, except for the analog
pins (AC, AT and AV). The Boundary Scan register of the AG pin can be used to enable/disable the gate
driver in software v9.0.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click
PDB Configuration.
A FlashPoint – Programming File Generator
window appears.
3. Click the
Specify I/O States During Programming
button to display the Specify I/O States
During Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
1-8
R e vi s i o n 3
