U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Solution 3
The board-level design must ensure that the reflected waveform at the pad does not exceed limits
provided in
This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used
for clamping, and the voltage must be limited by the bus switch, as shown in
Relying on the
diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 3
Fusion I/O Input
Off-Chip
Bus
Switch
IDTQS32X23
5.5 V
On-Chip
3.3 V
5.5 V
Requires a bus switch on the board,
LVTTL/LVCMOS 3.3 V I/Os.
Figure 2-105 •
Solution 3
Solution 4
Solution 4
Fusion I/O Input
Off-Chip
5.5 V
On-Chip
2.5 V On-Chip
Clamp
Diode
2.5 V
Rext1
Requires one board resistor.
Available for LVCMOS 2.5 V / 5.0 V.
Figure 2-106 •
Solution 4
Revision 3
2- 149
