U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Revision
Advance v0.8
(continued)
Changes
The
"1.5 V Voltage Regulator" section
was updated to add "or floating" in the
paragraph stating that an external pull-down is required on TRST to power down the
VR.
The
"1.5 V Voltage Regulator" section
was updated to include information on
powering down with the VR.
This sentence was updated in the
"No-Glitch MUX (NGMUX)" section
to delete GLA:
The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e.,
internal signal or GLC).
In
Table 2-13 • NGMUX Configuration and Selection Table,
10 and 11 were deleted.
The method to enable sleep mode was updated for bit 0 in
Table 2-16 • RTC
Control/Status Register.
S2 was changed to D2 in
Figure 2-39 • Read Waveform (Pipe Mode, 32-bit access)
for RD[31:0] was updated.
The definitions for bits 2 and 3 were updated in
Table 2-24 • Page Status Bit
Definition.
Figure 2-46 • FlashROM Timing Diagram
was updated.
Table 2-26 • FlashROM Access Time
is new.
Figure 2-55 • Write Access After Write onto Same Address, Figure 2-56 • Read
Access After Write onto Same Address,
and
Figure 2-57 • Write Access After Read
onto Same Address
are new.
Table 2-31 • RAM4K9
and
Table 2-32 • RAM512X18
were updated.
The VAREF and SAMPLE functions were updated in
Table 2-36 • Analog Block Pin
Description.
The title of
Figure 2-72 • Timing Diagram for Current Monitor Strobe
was updated to
add the word "positive."
The
"Gate Driver" section
was updated to give information about the switching rate
in High Current Drive mode.
The
"ADC Description" section
was updated to include information about the
SAMPLE and BUSY signals and the maximum frequencies for SYSCLK and
ADCCLK.
EQ 2
was updated to add parentheses around the entire expression in the
denominator.
Table 2-46 · Analog Channel Specifications
and
Table 2-47 · ADC Characteristics in
Direct Input Mode
were updated.
The note was removed from
Table 2-55 • Analog Multiplexer Truth Table—AV (x = 0),
AC (x = 1), and AT (x = 3).
Table 2-63 • Internal Temperature Monitor Control Truth Table
is new.
The
"Cold-Sparing Support" section
was updated to add information about cases
where current draw can occur.
Figure 2-104 • Solution 4
was updated.
Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings
was updated.
The
"GNDA Ground (analog)" section
and
"GNDAQ Ground (analog quiet)" section
were updated to add information about maximum differential voltage.
The
"V
AREF
Analog Reference Voltage" section
and
"VPUMP Programming Supply
Voltage" section
were updated.
Page
2-41
2-41
2-32
2-32
2-38
2-51
2-52
2-58
2-58
2-68–
2-70
2-71, 2-72
2-82
2-91
2-94
2-102
2-118,
2-121
2-131
2-132
2-143
2-147
2-153
2-224
2-226
Revision 3
5- 11
