U1AFS250-2FGG256YI
Model | U1AFS250-2FGG256YI |
Description | FPGA |
PDF file | Total 334 pages (File size: 18M) |
Chip Manufacturer | MICROSEMI |
Device Architecture
Table 2-73 •
Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os;
All I/O Bank Types (maximum drive strength and high slew selected)
Specification
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI
PCI-X
HSTL-I
HSTL-II
SSTL2-I
SSTL2-II
SSTL3-I
SSTL3-II
GTL+ 3.3 V
GTL+ 2.5 V
GTL 3.3 V
GTL 2.5 V
LVDS
LVPECL
Performance Up To
200 MHz
250 MHz
200 MHz
130 MHz
200 MHz
200 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
350 MHz
300 MHz
2- 14 0
R e visio n 3