U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
2- 13 8
1.5 V
I/O Bank Voltage (typical)
–
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
3.3 V PCI / PCI-X
GTL + (3.3 V)
GTL + (2.5 V)
GTL (3.3 V)
GTL (2.5 V)
HSTL Class I and II (1.5 V)
SSTL2 Class I and II (2.5 V)
SSTL3 Class I and II (3.3 V)
LVDS (2.5 V ± 5%)
LVPECL (3.3 V)
–
–
–
0.75 V
LVTTL/LVCMOS 3.3 V
1.25 V
1.00 V
0.80 V
1.50 V
1.00 V
0.80 V
Minibank Voltage (typical)
1.8 V
2.5 V
3.3 V
Table 2-71 •
Fusion Standard and Advanced I/O Features
Note:
White box: Allowable I/O standard combinations
Gray box: Illegal I/O standard combinations
R e visio n 3
