U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
DC and Power Characteristics
Table 3-13 •
Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings
1
C
LOAD
(pF)
Applicable to Pro I/O Banks
Single-Ended
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Voltage-Referenced
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
LVPECL
Applicable to Advanced I/O Banks
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Notes:
1. Dynamic power consumption is given for standard load and software-default drive strength and output slew.
2. PDC8 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
VCCI (V)
Static Power
PDC8 (mW)
2
Dynamic Power
PAC10 (µW/MHz)
3
35
35
35
35
10
10
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
474.70
270.73
151.78
104.55
204.61
204.61
10
10
10
10
20
20
30
30
30
30
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
–
–
–
–
7.08
13.88
16.69
25.91
26.02
42.21
24.08
13.52
24.10
13.54
26.22
27.22
105.56
116.60
114.87
131.76
–
–
2.5
3.3
7.70
19.42
89.62
168.02
35
35
35
35
10
10
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
468.67
267.48
149.46
103.12
201.02
201.02
3- 20
R e visio n 3
