U1AFS250-2FGG256YI
Model | U1AFS250-2FGG256YI |
Description | FPGA |
PDF file | Total 334 pages (File size: 18M) |
Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte order for read and write operations.
RD[17:0]
WD
RCLK
WCLK
WD[17:0]
RCLK
WCLK
RADD[J:0]
WADD[J:0]
FREN
REN
WEN
RAM
RD
FWEN
RBLK
REN
ESTOP
CNT 12
E
=
AFVAL
AFULL
FULL
WBLK
WEN
FSTOP
Reset
CNT 12
E
SUB 12
AEVAL
AEMPTY
EMPTY
=
Figure 2-47 •
Fusion RAM Block with Embedded FIFO Controller
Revision 3
RW[2:0]
WW[2:0]
RPIPE
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