U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Example: Calculation for Match Count
To put the Fusion device on standby for one hour using an external crystal of 32.768 KHz:
The period of the crystal oscillator is T
crystal
:
T
crystal
= 1 / 32.768 KHz = 30.518 µs
The period of the counter is T
counter
:
T
counter
= 30.518 us X 128 = 3.90625 ms
The Match Count for 1 hour is
Δtmatch:
Δtmatch
/ T
counter
= (1 hr X 60 min/hr X 60 sec/min) / 3.90625 ms = 921600 or 0xE1000
Using a 32.768 KHz crystal, the maximum standby time of the 40-bit counter is 4,294,967,296 seconds,
which is 136 years.
Table 2-16 •
RTC Control/Status Register
Bit
7
Name
rtc_rst
RTC Reset
1 – Resets the RTC
0 – Deassert reset on after two ACM_CLK cycle.
6
cntr_en
Counter Enable
1 – Enables the counter; rtc_rst must be deasserted as well. First
counter increments after 64 RTCCLK positive edges.
0 – Disables the crystal prescaler but does not reset the counter
value. Counter value can only be updated when the counter is
disabled.
5
vr_en_mat
Voltage Regulator Enable on Match
1 – Enables RTCMATCH and RTCPSMMATCH to output 1 when the
counter value equals the Match Register value. This enables the 1.5 V
voltage regulator when RTCPSMMATCH connects to the
RTCPSMMATCH signal in VRPSM.
0 – RTCMATCH and RTCPSMMATCH output 0 at all times.
4:3
xt_mode[1:0]
Crystal Mode
Controls RTCXTLMODE[1:0]. Connects to RTC_MODE signal in
XTLOSC. XTL_MODE uses this value when xtal_en is 1. See the
for mode configuration.
2
rst_cnt_omat
Reset Counter on Match
1 – Enables the sync clear of the counter when the counter value
equals the Match Register value. The counter clears on the rising
edge of the clock. If all the Match Registers are set to 0, the clear is
disabled.
0 – Counter increments indefinitely
1
0
rstb_cnt
xtal_en
Counter Reset, active Low
0 - Resets the 40-bit counter value
Crystal Enable
Controls RTCXTLSEL. Connects to SELMODE signal in XTLOSC.
0 – XTLOSC enables control by FPGA_EN; xt_mode is not used.
Sleep mode requires this bit to equal 0.
1 – Enables XTLOSC, XTL_MODE control by xt_mode
Standby mode requires this bit to be set to 1.
See the
for further details on
SELMODE configuration.
0
0
0
00
0
0
Description
Default
Value
2- 36
R e visio n 3
