U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
EN (b1)
EN (b2)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: ON
Transmitter 1: OFF
Transmitter 2: ON
Transmitter 2: OFF
Result: No Bus Contention
Figure 2-112 •
Timing Diagram (with skew circuit selected)
Weak Pull-Up and Weak Pull-Down Resistors
Fusion devices support optional weak pull-up and pull-down resistors for each I/O pin. When the I/O is
pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is
connected to GND. Refer to
for more information.
Slew Rate Control and Drive Strength
Fusion devices support output slew rate control: high and low. The high slew rate option is recommended
to minimize the propagation delay. This high-speed option may introduce noise into the system if
appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of
noise but adds some delays in the system. Low slew rate is recommended when bus transients are
expected. Drive strength should also be selected according to the design requirements and noise
immunity of the system.
The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V,
LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O
standards have a high output slew rate by default.
For Fusion slew rate and drive strength specifications, refer to the appropriate I/O bank table:
•
•
•
Fusion Standard I/O (Table
Fusion Advanced I/O (Table
Fusion Pro I/O (Table
lists the default values for the above selectable I/O attributes as well as those
that are preset for each I/O standard.
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R e visio n 3
