U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Table 2-99 •
Short Current Event Duration before Failure
Temperature
–40°C
0°C
25°C
70°C
85°C
100°C
Time before Failure
>20 years
>20 years
>20 years
5 years
2 years
6 months
Table 2-100 •
Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
Table 2-101 •
I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
LVTTL/LVCMOS (Schmitt trigger
disabled)
LVTTL/LVCMOS (Schmitt trigger
enabled)
HSTL/SSTL/GTL
LVDS/BLVDS/M-LVDS/LVPECL
Input Rise/Fall Time (min.)
No requirement
No requirement
Input Rise/Fall Time (max.)
10 ns*
Reliability
20 years (100°C)
Hysteresis Value (typ.)
240 mV
140 mV
80 mV
60 mV
No requirement, but input
20 years (100°C)
noise voltage cannot exceed
Schmitt hysteresis
10 ns*
10 ns*
10 years (100°C)
10 years (100°C)
No requirement
No requirement
Note:
*The maximum input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is
low, the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.
Microsemi recommends signal integrity evaluation/characterization of the system to ensure there is no excessive
noise coupling into input signals.
Revision 3
2- 177
