U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Table 2-96 •
I/O Output Buffer Maximum Resistances
1
(continued)
Standard
Applicable to Standard I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
2.5 V LVCMOS
2 mA
4 mA
6 mA
8 mA
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/soc/techdocs/models/ibis.html.
2. R
(PULL-DOWN-MAX)
= VOLspec / I
OLspec
3. R
(PULL-UP-MAX)
= (VCCImax – VOHspec) / IOHspec
Drive Strength
R
PULL-DOWN
(ohms)
2
100
100
50
50
100
100
50
50
200
100
200
R
PULL-UP
(ohms)
3
300
300
150
150
200
200
100
100
225
112
224
2 mA
4 mA
2 mA
Table 2-97 •
I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
R
(WEAK PULL-UP)1
(ohms)
VCCI
3.3 V
2.5 V
1.8 V
1.5 V
Notes:
1. R
(WEAK PULL-UP-MAX)
= (VCCImax – VOHspec) / I
WEAK PULL-UP-MIN
2. R
(WEAK PULL-DOWN-MAX)
= VOLspec / I
WEAK PULL-DOWN-MIN
R
(WEAK PULL-DOWN)2
(ohms)
Max.
45 k
55 k
70 k
90 k
Min.
10 k
12 k
17 k
19 k
Max.
45 k
74 k
110 k
140 k
Min.
10 k
11 k
18 k
19 k
2- 17 4
R e visio n 3
