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U1AFS250-2FGG256YI

Model	U1AFS250-2FGG256YI
Description	FPGA
PDF file	Total 334 pages (File size: 18M)
Chip Manufacturer	MICROSEMI

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5 – Datasheet Information

List of Changes

The following table lists critical changes that were made in each revision of the Fusion datasheet.

Revision

Revision 3

(August 2012)

Changes

Microblade U1AFS250 and U1AFS1500 devices were added to the product tables.

A sentence pertaining to the analog I/Os was added to the

"Specifying I/O States

During Programming" section

(SAR 34831).

The

"RC Oscillator" section

was revised to correct a sentence that did not

differentiate accuracy for commercial and industrial temperature ranges, which is

given in

Table 2-9 • Electrical Characteristics of RC Oscillator

(SAR 33722).

Figure 2-57 • FIFO Read

and

Figure 2-58 • FIFO Write

are new (SAR 34840).

The first paragraph of the

"Offset" section

was removed; it was intended to be

replaced by the paragraph following it (SAR 22647).

IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected in

Table 2-86 •

Summary of Maximum and Minimum DC Input and Output Levels Applicable to

Commercial and Industrial Conditions

(SAR 39813).

The drive strength, IOL, and IOH for 3.3 V GTL and 2.5 V GTL were changed from

25 mA to 20 mA in the following tables (SAR 37373):

Table 2-86 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions,

Table 2-92 • Summary of I/O Timing Characteristics – Software Default Settings

Table 2-96 • I/O Output Buffer Maximum Resistances 1

Table 2-138 • Minimum and Maximum DC Input and Output Levels

Table 2-141 • Minimum and Maximum DC Input and Output Levels

The following sentence was deleted from the

"2.5 V LVCMOS" section

(SAR 34800):

"It uses a 5 V–tolerant input buffer and push-pull output buffer."

Corrected the inadvertent error in maximum values for LVPECL VIH and VIL and

revised them to "3.6" in

Table 2-171 • Minimum and Maximum DC Input and Output

Levels,

making these consistent with

Table 3-1 • Absolute Maximum Ratings,

and

Table 3-4 • Overshoot and Undershoot Limits 1

(SAR 37687).

The maximum frequency for global clock parameter was removed from

Table 2-5 •

AFS1500 Global Resource Timing

through

Table 2-8 • AFS090 Global Resource

Timing

because a frequency on the global is only an indication of what the global

network can do. There are other limiters such as the SRAM, I/Os, and PLL.

SmartTime software should be used to determine the design frequency (SAR

36955).

Revision 2

(March 2012)

The phrase "without debug" was removed from the

"Soft ARM Cortex-M1 Fusion

Devices (M1)" section

(SAR 21390).

The

"In-System Programming (ISP) and Security" section, "Security" section, "Flash

Advantages" section,

and

"Security" section

were revised to clarify that although no

existing security measures can give an absolute guarantee, Microsemi FPGAs

implement the best security available in the industry (SAR 34679).

Page

–

I, 1-2,

Revision 3

5 -1

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