U1AFS250-2FGG256YI
Model | U1AFS250-2FGG256YI |
Description | FPGA |
PDF file | Total 334 pages (File size: 18M) |
Chip Manufacturer | MICROSEMI |
Device Architecture
t
EOUT
D Q
E
CLK
t
ZL
, t
ZH
, t
HZ
, t
LZ
, t
ZLS
, t
ZHS
EOUT
D Q
D
CLK
t
EOUT
= MAX(t
EOUT
(R). t
EOUT
(F))
VCC
D
VCC
E
50%
t
EOUT (R)
50%
t
ZL
DOUT
PAD
I/O Interface
50%
t
EOUT (F)
VCC
50%
t
HZ
t
ZH
EOUT
PAD
50%
VCCI
V
trip
50%
t
LZ
V
trip
90% VCCI
VOL
10% VCCI
VCC
D
VCC
E
50%
t
EOUT (R)
50%
t
ZLS
V
trip
VOL
50%
VCC
t
EOUT (F)
50%
VOH
50%
t
ZHS
V
trip
EOUT
PAD
Figure 2-118 •
Tristate Output Buffer Timing Model and Delays (example)
2- 16 6
R e visio n 3