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U1AFS250-2FGG256YI

U1AFS250-2FGG256YI

Model U1AFS250-2FGG256YI
Description FPGA
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Fusion Family of Mixed Signal FPGAs
Revision
v2.0, Revision 1
(continued)
Changes
The
is new.
was significantly updated.
was significantly updated.
In
note 2 was updated.
In
note 1 was updated.
In
bit 89 was removed.
The data in the 2.5 V LCMOS and LVCMOS 2.5 V / 5.0 V rows were updated in
In
LVCMOS
1.5 V, for OUT_DRIVE 2, was changed from a dash to a check mark.
The
definition was changed from "A 1.5 V
analog power supply input should be used to provide this input"
to
"1.5 V clean analog power supply input for use by the 1.5 V portion of the analog
circuitry."
In the
pin description, the following text
was changed from "VCC33PMP should be powered up before or simultaneously
with VCC33A"
to
"VCC33PMP should be powered up simultaneously with or after VCC33A."
The
was updated to include
information about when to power the pin.
In the
FIPS-192 was incorrect and changed to
FIPS-197.
The note in
was updated.
For 1.5 V LVCMOS, the VIL and VIH parameters, 0.30 * VCCI was changed to 0.35 *
VCCI and 0.70 * VCCI was changed to 0.65 * VCCI in
and
In
the VIH max column was
updated.
was updated to include notes 3 and 4. The
temperature ranges were also updated in notes 1 and 2.
The titles in
to
were updated to "VCCI = I/O Standard Dependent."
Page
to
to
Revision 3
5 -5
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