U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
CLK
t
DDRISUD
Data
1
2
3
4
5
6
7
t
DDRIHD
8
t
DDRIRECCLR
CLR
t
DDRIREMCLR
t
DDRICLKQ1
t
DDRICLR2Q1
Out_QF
t
DDRICLR2Q2
Out_QR
3
2
4
t
DDRICLKQ2
5
7
6
9
Figure 2-143 •
Input DDR Timing Diagram
Timing Characteristics
Table 2-180 •
Input DDR Propagation Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
DDRICLKQ1
t
DDRICLKQ2
t
DDRISUD
t
DDRIHD
t
DDRICLR2Q1
t
DDRICLR2Q2
t
DDRIREMCLR
t
DDRIRECCLR
t
DDRIWCLR
t
DDRICKMPWH
t
DDRICKMPWL
F
DDRIMAX
Description
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
–2
0.39
0.27
0.28
0.00
0.57
0.46
0.00
0.22
0.22
0.36
0.32
1,404
–1
0.44
0.31
0.32
0.00
0.65
0.53
0.00
0.25
0.25
0.41
0.37
1,048
Std.
0.52
0.37
0.38
0.00
0.76
0.62
0.00
0.30
0.30
0.48
0.43
1,232
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 3
2- 223
