U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-156 •
Minimum and Maximum DC Input and Output Levels
SSTL2 Class I
Drive
Strength
15 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
VIL
Min.
V
Max.
V
Min.
V
VIH
Max.
V
3.6
VOL
Max.
V
0.54
VOH
Min.
V
IOL IOH IOSL IOSH IIL
1
Max.
mA mA mA
3
15
87
IIH
2
Max.
mA
3
µA
4
µA
4
83
10
10
–0.3 VREF – 0.2 VREF + 0.2
VCCI – 0.62 15
SSTL2
Class I
Test Point
25
VTT
50
30 pF
Figure 2-130 •
AC Loading
Table 2-157 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
VREF – 0.2
Input High (V)
VREF + 0.2
Measuring Point* (V)
1.25
VREF (typ.) (V)
1.25
VTT (typ.) (V)
1.25
C
LOAD
(pF)
30
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
Timing Characteristics
Table 2-158 •
SSTL 2 Class I
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
Speed
Grade
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
t
DP
2.13
1.81
1.59
t
DIN
0.04
0.04
0.03
t
PY
1.33
1.14
1.00
t
EOUT
0.43
0.36
0.32
t
ZL
2.17
1.84
1.62
t
ZH
1.85
1.57
1.38
t
LZ
t
HZ
t
ZLS
4.40
3.74
3.29
t
ZHS
4.08
3.47
3.05
Units
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
2- 20 8
R e visio n 3
