U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting
deassertion (disable) time.
Output Enable
(from FPGA core)
ENABLE (IN)
ENABLE (OUT)
MUX
Skew Circuit
I/O Output
Buffers
Skew Select
Figure 2-107 •
Block Diagram of Output Enable Path
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
Figure 2-108 •
Timing Diagram (option1: bypasses skew circuit)
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typical)
Less than
0.1 ns
Figure 2-109 •
Timing Diagram (option 2: enables skew circuit)
2- 15 2
R e visio n 3
