U1AFS250-2FGG256YI
| Model | U1AFS250-2FGG256YI |
| Description | FPGA |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
CCC
Bank 0
CCC
Bank 1
CCC
Up to five VREF
minibanks within
an I/O bank
VREF signal scope is
between 8 and 18 I/Os.
Common VREF
signal for all I/Os
in VREF minibanks
GND
GND
VCC
VCCI
VCC
VCCI
Figure 2-99 •
Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)
Table 2-67 •
I/O Standards Supported by Bank Type
I/O Bank
Standard I/O
Single-Ended I/O Standards
LVTTL/LVCMOS 3.3 V, LVCMOS –
2.5 V / 1.8 V / 1.5 V, LVCMOS
2.5/5.0 V
Differential I/O
Standards
–
Voltage-Referenced
Hot-
Swap
Yes
Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL
2.5 V / 1.8 V / 1.5 V, LVCMOS
LVDS
2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-
X
Pro I/O
LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL
2.5 V / 1.8 V / 1.5 V, LVCMOS
LVDS
2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-
X
I/O
I/O
I/O Pad
I/O
I/O
If needed, the VREF for a given
minibank can be provided by
any I/O within the minibank.
I/O
and –
and GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V,
HSTL Class I and II, SSTL2 Class I
and II, SSTL3 Class I and II
I/O
I/O
I/O
–
Yes
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R e visio n 3
