U1AFS600-2FG256YI
Model | U1AFS600-2FG256YI |
Description | Field Programmable Gate Array, |
PDF file | Total 334 pages (File size: 18M) |
Chip Manufacturer | MICROSEMI |
Device Architecture
Timing Diagrams
t
CAL
= 3,840 t
ADCCLK
*
SYSCLK
t
RECCLR
ADCRESET
t
SUTVC
TVC[7:0]
t
CK2QCAL
CALIBRATE
Note:
*Refer to
for the calculation on the period of ADCCLK, t
ADCCLK
.
Figure 2-89 •
Power-Up Calibration Status Signal Timing Diagram
t
REMCLR
t
HDTVC
t
CK2QCAL
t
MINSYSCLK
SYSCLK
t
SUADCSTART
ADCSTART
t
SUMODE
MODE[3:0]
t
SUTVC
TVC[7:0]
t
SUSTC
STC[7:0]
t
SUVAREFSEL
VAREF
t
SUCHNUM
CHNUMBER[7:0]
Figure 2-90 •
Input Setup Time
t
MPWSYSCLK
t
HDADCSTART
t
HDMODE
t
HDTVC
t
HDSTC
t
HDVAREFSEL
t
HDCHNUM
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