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Home > Data Sheet > U1AFS600-2FG256YI
U1AFS600-2FG256YI

U1AFS600-2FG256YI

Model U1AFS600-2FG256YI
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Device Architecture
Table 2-81 •
Fusion Pro I/O Default Attributes
SCHMITT_TRIGGER (input only)
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
SKEW (tribuf and bibuf only)
I/O Standards
LVTTL/LVCMO
S 3.3 V
LVCMOS 2.5 V
LVCMOS
2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
PCI-X (3.3 V)
GTL+ (3.3 V)
GTL+ (2.5 V)
GTL (3.3 V)
GTL (2.5 V)
HSTL Class I
HSTL Class II
SSTL2
Class I and II
SSTL3
Class I and II
LVDS, BLVDS,
M-LVDS
LVPECL
SLEW
(output only)
Refer to the following
tables for more
information:
OUT_DRIVE
(output only)
Refer to the following
tables for more
information:
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
35 pF
35 pF
35 pF
35 pF
35 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
20 pF
20 pF
30 pF
30 pF
0 pF
0 pF
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
2- 15 6
R e visio n 3
IN_DELAY_VAL (input only)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT_LOAD (output only)
IN_DELAY (input only)
COMBINE_REGISTER
RES_PULL
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