U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Timing Characteristics
Table 2-1 •
Combinatorial Cell Propagation Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
AND2
NAND2
OR2
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Equation
Y = !A
Y=A·B
Y = !(A · B)
Y=A+B
Y = !(A + B)
Y=A
⊕
B
Y = MAJ(A, B, C)
Y=A
⊕
B
⊕
C
Y = A !S + B S
Y=A·B·C
Parameter
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
–2
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
–1
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
Std.
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Sample VersaTile Specifications—Sequential Module
The Fusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library (Figure
For more details, refer to the
Revision 3
2 -5
