U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-141 •
Minimum and Maximum DC Input and Output Levels
2.5 GTL
Drive
Strength
20 mA
3
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
VIL
Min.
V
–0.3
Max.
V
Min.
V
VIH
Max.
V
3.6
VOL
Max.
V
0.4
VOH
Min.
V
–
IOL IOH
mA
20
mA
20
IOSL
Max.
mA
3
124
IOSH
Max.
mA
3
169
IIL
1
µA
4
10
IIH
2
µA
4
10
VREF – 0.05 VREF + 0.05
VTT
GTL
Test Point
10 pF
25
Figure 2-125 •
AC Loading
Table 2-142 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
VREF – 0.05
Input High (V)
VREF + 0.05
Measuring Point* (V)
0.8
VREF (typ.) (V)
0.8
VTT (typ.) (V)
1.2
C
LOAD
(pF)
10
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
Timing Characteristics
Table 2-143 •
2.5 V GTL
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 0.8 V
Speed
Grade
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
t
DP
2.13
1.81
1.59
t
DIN
0.04
0.04
0.03
t
PY
2.46
2.09
1.83
t
EOUT
0.43
0.36
0.32
t
ZL
2.16
1.84
1.61
t
ZH
2.13
1.81
1.59
t
LZ
t
HZ
t
ZLS
4.40
3.74
3.28
t
ZHS
4.36
3.71
3.26
Units
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 3
2- 203
