U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Table 2-15 •
Memory Map for RTC in ACM Register and Description
ACMADDR
0x40
0x41
0x42
0x43
0x44
0x48
0x49
0x4A
0x4B
0x4C
0x50
Register Name
COUNTER0
COUNTER1
COUNTER2
COUNTER3
COUNTER4
MATCHREG0
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
MATCHBIT0
Description
Counter bits 7:0
Counter bits 15:8
Counter bits 23:16
Counter bits 31:24
Counter bits 39:32
Match register bits 7:0
Match register bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual match bits 7:0
The output of the XNOR gates
0 – Not matched
1 – Matched
0x51
0x52
0x53
0x54
0x58
MATCHBIT1
MATCHBIT2
MATCHBIT3
MATCHBIT4
CTRL_STAT
Individual match bits 15:8
Individual match bits 23:16
Individual match bits 31:24
Individual match bits 29:32
Control (write/read) / Status Refer to
(read only) register bits
for details.
0x00
0x00
0x00
0x00
0x00
The RTC comparison bits
Use
Used to preload the counter to
a specified start point.
Default
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Voltage Regulator and Power System Monitor (VRPSM)
The VRPSM macro controls the power-up state of the FPGA. The power-up bar (PUB) pin can turn on
the voltage regulator when set to 0. TRST can enable the voltage regulator when deasserted, allowing
the FPGA to power-up when user want access to JTAG ports. The inputs VRINITSTATE and
RTCPSMMATCH come from the flash bits and RTC, and can also power up the FPGA.
VRPSM
VRPU
VRINITSTATE
RTCPSMMATCH
VREN*
PUB
TRST*
FPGAGOOD
PUCORE
Note:
*Signals are hardwired internally and do not exist in the macro core.
Figure 2-30 •
VRPSM Macro
Revision 3
2- 37
