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U1AFS600-2FG256YI

U1AFS600-2FG256YI

Model U1AFS600-2FG256YI
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Device Architecture
Output Register
t
OCKMPWH
t
OCKMPWL
50%
50%
t
OSUD
t
OHD
Data_out
1
50%
0
50%
50%
50%
50%
50%
50%
CLK
Enable
50%
t
OHE
50%
t
OWPRE
t
ORECPRE
50%
t
OREMPRE
50%
t
OREMCLR
50%
Preset
t
OSUE
t
OWCLR
Clear
t
OPRE2Q
DOUT
50%
t
OCLKQ
50%
t
OCLR2Q
50%
50%
t
ORECCLR
50%
Figure 2-140 •
Output Register Timing Diagram
Timing Characteristics
Table 2-177 •
Output Data Register Propagation Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
OCLKQ
t
OSUD
t
OHD
t
OSUE
t
OHE
t
OCLR2Q
t
OPRE2Q
t
OREMCLR
t
ORECCLR
t
OREMPRE
t
ORECPRE
t
OWCLR
t
OWPRE
t
OCKMPWH
t
OCKMPWL
Description
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data
Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
–2
0.59
0.31
0.00
0.44
0.00
0.80
0.80
0.00
0.22
0.00
0.22
0.22
0.22
0.36
0.32
–1
0.67
0.36
0.00
0.50
0.00
0.91
0.91
0.00
0.25
0.00
0.25
0.25
0.25
0.41
0.37
Std.
0.79
0.42
0.00
0.59
0.00
1.07
1.07
0.00
0.30
0.00
0.30
0.30
0.30
0.48
0.43
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
2- 22 0
R e visio n 3
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