U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
5 V Input Tolerance
I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V, and
LVCMOS 2.5 V configurations are used (see
for more details). There are four
recommended solutions (see
to
for details of board and macro
setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of limiting the
voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any
voltage above 3.6 V may cause long-term gate oxide failures.
Solution 1
The board-level design needs to ensure that the reflected waveform at the pad does not exceed the limits
provided in
This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI / PCI-X configuration, but the internal diode should not be
used for clamping, and the voltage must be limited by the two external resistors, as explained below.
Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
The following are some examples of possible resistor values (based on a simplified simulation model
with no line effects and 10
Ω
transmitter output resistance, where Rtx_out_high = (VCCI – VOH) / IOH,
Rtx_out_low = VOL / IOL).
Example 1 (high speed, high current):
Rtx_out_high = Rtx_out_low = 10
Ω
R1 = 36
Ω
(±5%), P(r1)min = 0.069
Ω
R2 = 82
Ω
(±5%), P(r2)min = 0.158
Ω
Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 mA
t
RISE
= t
FALL
= 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin)
t
RISE
= t
FALL
= 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin)
Example 2 (low–medium speed, medium current):
Rtx_out_high = Rtx_out_low = 10
Ω
R1 = 220
Ω
(±5%), P(r1)min = 0.018
Ω
R2 = 390
Ω
(±5%), P(r2)min = 0.032
Ω
Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 mA
t
RISE
= t
FALL
= 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin)
t
RISE
= t
FALL
= 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin)
Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the
voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range of
Vin_dc(rx) must be assured for any combination of transmitter supply (5 V ± 0.5 V), transmitter output
resistance, and board resistor tolerances.
Revision 3
2- 147
